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UMC
is the foundry leader in 65nm process technology, having delivered
the foundry industry's first 65nm customer products in June
of 2005. UMC's 65nm technology supports high performance and
low power requirements. Leading-edge 65nm is now fully qualified
and in production for customer products, which include ICs
that utilize advanced triple gate oxide with 11 metal layers.
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| 65nm
Brochure (pdf,
1,027kb) |
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Key
Features of UMC 65-nanometer technology
- Integrated Flows for Logic, Mixed Mode, and RF
- 193nm Litho for All Critical Layers
- Mobility Enhancement Techniques
- Retrograde Twin Well (Deep N-Well Option)
- Multiple Vt Options
- Enhanced Nitrided Gate Oxide
- 40nm Min. Poly Length
- NiSi Process
- 1P10M Cu/Low K (k = 2.9)
- 6T/8T e-SRAM Bit Cells; 1T-RAM (URAMTM) Option
(0.12um2)
- e-Fuse Option
- Wire Bond/ Flip Chip Options
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65nm SoC Solutions
UMC's 65-nanometer SoC solution begins with a flexible technology
design platform. Customers are able to choose the process device
options that are optimized for their specific application, such
as Standard Performance (SP), Low Leakage (LL) or Low Power (LP) transistors.
The high performance characteristics of UMC's 65nm SP process
enable designers to utilize the technology to power a broad
range of applications from consumer products to graphics ICs.
Technology options can then be implemented including mixed signal/RFCMOS
and embedded memories to further customize the process. |
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Technology
to Meet Broad Applications
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65nm Logic/MS1) Devices
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