Today's advanced process and package technologies pose challenges
to SoC designers in terms of reliability, cost, and performance.
UMC has partnered with industry-leading vendors to effectively
address these challenges to offer customer benefits such as
established and verified design rules, verification of low-k
wafer materials and structures, optimized package materials
and parameters, and enhanced reliability performance. Sophisticated
test vehicles are another advantage achieved through UMC's methodology.
Customer endorsed qualification flows
and specs
Fig. 1: UMC's methodology to deliver solutions to customers'
packaging needs
UMC also works with world leading packaging houses
to provide silicon proven packaging solutions. Starting from
test-chip and technology development with assembly support through
its packaging partners the silicon proven packaging solutions
can meet the requirements of demanding designs, meet stringent
qualification criteria, and ensure reliability for sophisticated
chips such as those utilizing low-k dielectric materials for
Cu interconnect. All vendors are ISO9000 certified and must
meet UMC set criteria regarding yields and cycle time.
Fig. 2: UMC's packaging solution development for advanced package
performance & qualities
Solutions
Capability
Bump / Flip Chip
Solder: 8" & 12" wafer
162um solder bump pitch
Wire Bond
45um in-line pad pitch, high pin count
BOAC
65nm & 90nm low-k
MCP / SiP
Stack die, POP & PIP
Lead Free Package
Wire Bond
Flip Chip
Fig 3: UMC's solutions to address various packaging challenges
Test/Package
Partners
UMC's major test and package subcontractors are located in Taiwan
and throughout Asia. The close proximity of UMC's test and package
partners to UMC's own facilities creates synergies that enable
faster service and greater flexibility.
UMC's partners for testing and packaging include: ASE/ASE Test,
Amkor, Ardentec, Global Testing Corp., KYEC, SPIL, StatsChipPAC,
UST, UTAC, and Winstek.
